1. Field of the Invention
The present invention generally relates to the field of fabrication of semiconductor devices. More particularly, the present invention relates to the field of fabrication of bipolar transistors.
2. Related Art
In addition to high speed, low noise, and high current driver advantages of bipolar transistors, circuits used in modern electronic devices also require low power consumption and high process integration typically provided by metal-oxide semiconductor (“MOS”) transistors. In an attempt to combine the benefits of NPN and PNP bipolar transistors with the benefits of MOS transistors, such as P and N channel field effect transistors, semiconductor manufacturers fabricate circuits comprising bipolar and MOS transistors on the same substrate of a die using Bipolar Complementary-Metal-Oxide-Semiconductor (“BiCMOS”) technology.
To reduce manufacturing cost, semiconductor manufacturers commonly form lateral PNP transistors such that they are compatible with process flows adapted to fabricate NPN devices or MOS devices. For example, a base of a lateral PNP transistor can be formed utilizing a thin epitaxial N layer that is also utilized to form a collector of an NPN transistor. However, the thin epitaxial layer utilized in the fabrication of a collector of a high performance NPN transistor results in a lateral PNP transistor having an unacceptable gain when the thin epitaxial layer is also utilized to form the base of the lateral PNP transistor. Thus, semiconductor manufacturers are challenged to provide a lateral PNP transistor having an acceptable gain such that the fabrication of the lateral PNP transistor is compatible with the process flow utilized to fabricate an NPN transistor.
FIG. 1 shows a cross-sectional view of a structure that includes a conventional exemplary lateral PNP transistor formed in a manner compatible with a process flow utilized to fabricate an NPN and MOS devices. Structure 100 includes conventional lateral PNP transistor 102, substrate 104, buried layer 106, and silicide layer 108. Conventional lateral PNP transistor 102 includes base 110, emitter 112, and collectors 114 and 116.
As shown in FIG. 1, buried layer 106 comprises N+ type material and is formed in substrate 104 in a manner known in the art. Also shown in FIG. 1, base 110 is situated over buried layer 106 and can be, for example, N type single crystal silicon that may be formed using a dopant diffusion process in a manner known in the art. Emitter 112 is situated over base 110 and may comprise a P+ type material such as P+ type silicon-germanium (“SiGe”), which may be deposited epitaxially in a low-pressure chemical vapor deposition (“LPCVD”) process. Further shown in FIG. 1, silicide layer 108 is situated over emitter 112 and provides an ohmic contact for emitter 112 as known in the art. Also shown in FIG. 1, collectors 114 and 116 are formed in substrate 104 in a manner known in the art and can comprise P type material.
The operation of conventional exemplary lateral PNP transistor 102 will now be discussed. When base-emitter junction 118 is forward biased in an active mode of operation, the beta, i.e. the gain, of conventional exemplary lateral PNP transistor 102 is inversely proportional to base current at constant collector current. Thus, at constant collector current, a decrease in base current will cause the beta to increase. By way of background, base current in a bipolar transistor comprises two dominant components: a space charge recombination current that occurs at depletion region of the base-emitter junction and a diffusion current that is caused by an electron concentration gradient in the emitter of the bipolar transistor.
In the active mode, a high electron concentration exists at the edge of emitter side of base-emitter junction 118 of conventional lateral PNP transistor 102 as a result of forward bias at base-emitter junction 118, among other things. However, at the interface between silicide layer 108 and emitter 112, i.e. interface 120, the electron concentration is approximately zero as a result of the ohmic contact formed by silicide layer 108. Thus, an electron concentration gradient is formed as a result of high electron concentration at base-emitter junction 118 and approximately zero electron concentration at interface 120. The resulting higher electron concentration gradient causes higher electron diffusion current to flow in emitter 112, which increases base current. An increase in base current results in an undesirable decrease in gain, or beta, of conventional exemplary lateral PNP transistor 102, since the gain of lateral PNP transistor 102 is inversely proportional to base current as discussed above. The amount of electron diffusion current flow, and thus the amount of increase in base current, is determined by the steepness of the electron concentration gradient. An increase in steepness of the electron concentration gradient, for example, causes an increase in electron diffusion current.
One approach utilized to increase the gain of a lateral PNP transistor, such as conventional exemplary lateral PNP transistor 102, is to fabricate a thin oxide layer over emitter 112 and then fabricate a polysilicon layer between the thin oxide layer and silicide layer 108. The thin oxide layer functions as an electron barrier that causes an increase in electron concentration at the interface between emitter 112 and the thin oxide layer, which results in a decrease in the steepness of the electron concentration gradient in emitter 112. As a result, base current decreases, which causes the gain of exemplary lateral PNP transistor 102 to increase. However, the above approach results in an undesirable increase in process steps and fabrication cost associated with forming both the thin oxide layer and the polysilicon layer.
Thus, there is a need in the art for a bipolar transistor, such as a lateral PNP bipolar transistor, to have an increased gain without suffering an undesirable increase in process steps and fabrication cost.